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Data Sheet, Rev. 1.00, Feb. 2006
Cover Page
HYS72T64000HP-[3S/3.7]-A HYS72T1280x0HP-[3S/3.7]-A HYS72T256x20HP-[3S/3.7]-A HYS72T256040HP-[3S/3.7]-A
240-Pin Registered DDR2 SDRAM Modules with parity
DDR2 SDRAM RDIMM SDRAM RoHs Compliant
Memory Products
Imprint Edition 2006-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Revision History HYS72T64000HP-[3S/3.7]-A, HYS72T1280x0HP-[3S/3.7]-A, HYS72T256x20HP-[3S/3.7]-A, HYS72T256040HP-[3S/3.7]-A Revision History: 2006-02, Rev. 1.00 Previous Version: Page Subjects (major changes since last revision) Initial Document
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Template: mp_a4_s_rev321 / 3 / 2005-10-05
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Table of Contents
Table of Contents
1 1.1 1.2 2 2.1 2.2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 3.4.1 3.4.2 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 27 27 29 35 36 40 41
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Data Sheet
4
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
240-Pin Registered DDR2 SDRAM Modules with parity DDR2 SDRAM
HYS72T64000HP-[3S/3.7]-A HYS72T1280x0HP-[3S/3.7]-A HYS72T256x20HP-[3S/3.7]-A HYS72T256040HP-[3S/3.7]-A
1
Overview
This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules with parity product family and describes its main characteristics.
1.1
* *
Features
* * * * * * * * * Registered DIMM Parity bit for address and control bus Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM Based on standard reference layouts Raw Card "AF", "C-H", "B-G", "J", "L" and "N" RDIMM with parity Dimensions (nominal): 30.00 mm high, 133.35 mm wide RoHS compliant products1)
*
*
*
240-pin PC2-5300 and PC2-4200 DDR2 SDRAM memory modules One rank 64M x 72, 128M x 72, two ranks 128M x 72, 256M x 72, and four ranks 256M x 72 module organization and 64M x 8, 128M x 4 chip organization 512 MByte, 1GByte and 2GByte module built with 512-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize packages. Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications as well. Performance for PC2-5300-555
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-3S PC2-5300 5-5-5
Unit -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
333 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
5
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Overview
Table 2
Performance for PC2-4200-444 -3.7 PC2-4200 4-4-4 @CL5 @CL4 @CL3 Unit -- MHz MHz MHz ns ns ns ns
Product Type Speed Code Speed Grade max. Clock Frequency
min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time Table 3 Performance for PC2-3200-333
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-5 PC2-3200 3-3-3
Units -- MHz MHz MHz ns ns ns ns
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
200 200 200 15 15 40 55
Data Sheet
6
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Overview
1.2
Description
The INFINEON HYS72T[64/128/256]xx0]HP-[3S/3.7]-A module family are Registered DIMM (RDIMM with parity) with 30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M x 72 (512 MByte), 128M x 72 (1 GByte) and 256M x 72 (2 GByte) organization and density, intended for mounting into 240-Pin connector sockets. The memory array is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Table 4 PC2-5300
Ordering Information for RoHS Compliant Products Compliance Code2) 512 MB 1Rx8 PC2-5300P-555-12-F0 1 GB 1Rx4 PC2-5300P-555-12-H0 1 GB 2Rx8 PC2-5300P-555-12-G0 2 GB 2Rx4 PC2-5300P-555-12-L0 2 GB 2Rx4 PC2-5300P-555-12-J1 2 GB 4Rx8 PC2-5300P-555-12-N0 512 MB 1Rx8 PC2-4200P-444-12-F0 1 GB 1Rx4 PC2-4200P-444-12-H0 1 GB 2Rx8 PC2-4200P-444-12-G0 2 GB 2Rx4 PC2-4200P-444-12-J1 2 GB 4Rx8 PC2-4200P-444-12-N0 Description 1 Rank, ECC 1 Rank, ECC SDRAM Technology 512 Mbit (x8) 512 Mbit (x4)
Product Type1) HYS72T64000HP-3S-A HYS72T128000HP-3S-A HYS72T128020HP-3S-A HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A PC2-4200 HYS72T64000HP-3.7-A HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A
2 Ranks, ECC 512 Mbit (x8) 2 Ranks, ECC 512 Mbit (x4) 2 Ranks, ECC 512 Mbit (x4) 4 Ranks, ECC 512 Mbit (x8) 1 Rank, ECC 1 Rank, ECC 512 Mbit (x8) 512 Mbit (x4)
2 Ranks, ECC 512 Mbit (x8) 2 Ranks, ECC 512 Mbit (x4) 4 Ranks, ECC 512 Mbit (x8)
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T128000HP-3.7-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200P-444- 12-H0", where 4200P means Registered DIMM parity modules with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "H"
Data Sheet
7
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Overview
Table 5 DIMM Density 512 MB 1 GB 1 GB 2 GB 2 GB Table 6
Address Format Module Organization 64M x 72 128M x 72 128M x 72 256M x 72 256M x 72 Memory Ranks 1 1 2 2 4 ECC/ Non-ECC ECC ECC ECC ECC ECC # of SDRAMs 9 18 18 36 36 # of row/bank/columns bits Raw Card 14/2/10 14/2/10 14/2/10 14/2/10 14/2/10 A-F C-H B-G J, L N
Components on Modules 1) DRAM Components2) HYB18T512800AF HYB18T512400AF HYB18T512800AF HYB18T512400AF HYB18T512400AF HYB18T512800AF DRAM Density 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit 512 Mbit DRAM Organization 64M x 8 128M x 4 64M x 8 128M x 4 128M x 4 64M x 8
Product Type2) HYS72T64000HP HYS72T128000HP HYS72T128020HP HYS72T256020HP HYS72T256220HP HYS72T256040HP
1) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet. 2) Green Product
Data Sheet
8
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
2
2.1
Pin Configuration and Block Diagrams
Pin Configuration
explained in Table 8 and Table 9 respectively. The pin numbering is depicted in Figure 1.
The pin configuration of the Registered DDR2 SDRAM DIMM is listed by function in Table 7 (240 pins). The abbreviations used in columns Pin and Buffer Type are Table 7 Pin Configuration of RDIMM Name Pin Buffer Type Type I I SSTL SSTL
Pin or Ball No. Clock Signals 185 186
Function
CK0 CK0
Clock Signal CK0, Complementary Clock Signal CK0 The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Clock Enables 1:0 Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. Note: 2-Ranks module Not Connected Note: 1-Rank module
52 171
CKE0 CKE1
I I
SSTL SSTL
NC Control Signals 193 76 S0 S1
NC
--
I I
SSTL SSTL
Chip Select Rank 1:0 Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state. Note: 2-Ranks module Not Connected Note: 1-Rank module Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) When sampled at the cross point of the rising edge of CK, and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM.
NC 192 74 73 RAS CAS WE
NC I I I
-- SSTL SSTL SSTL
Data Sheet
9
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name RESET Pin Buffer Type Type I CMOS Function Register Reset The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When LOW, all register outputs will be driven LOW and the PLL clocks to the DRAMs and the register(s) will be set to low-level. The PLL will remain synchronized with the input clock. Bank Address Bus 1:0 Selects internal SDRAM memory bank Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Not Connected Less than 1Gb DDR2 SDRAMS Address Bus 12:0, Address Signal 10/AutoPrecharge During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define which bank to precharge. Address Signal 13 Not Connected Note: Non CA parity modules based on 256 Mbit component 174 A14 NC 173 A15 NC I NC I NC SSTL -- SSTL -- Address Signal 14 Note: CA Parity module Not Connected Note: Non CA parity module Address Signal 14 Note: CA Parity module Not Connected Note: Non CA parity module
Pin or Ball No. 18
Address Signals 71 190 54 BA0 BA1 BA2 NC 188 183 63 182 61 60 180 58 179 177 70 57 176 196 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC I I I I I I I I I I I I I I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL --
Data Sheet
10
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL 11 Rev. 1.00, 2006-02 04212005-MF7V-DNO1 Function
Pin or Ball No. Data Signals 3 4 9 10 122 123 128 129 12 13 21 22 131 132 140 141 24 25 30 31 143 144 149 150 33 34 39 40 152 153 158 159 80 81 86 87 199 200 205 Data Sheet
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38
Data Bus 63:0 Data Input/Output pins
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Check Bits 7:0 Check Bit Input / Output pins Note: NC on Non-ECC module Function Data Bus 63:0
Pin or Ball No. 206 89 90 95 96 208 209 214 215 98 99 107 108 217 218 226 227 110 111 116 117 229 230 235 236 Check Bits 42 43 48 49 161 162 167 168
Data Sheet
12
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function
Pin or Ball No. Data Strobe Bus 7 6 16 15 28 27 37 36 84 83 93 92 105 104 114 113 46 45 125 126 134 135 146 147 155 156 202 203 211 212 223 224 232 233 164 165
DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DQS8 DQS8 DQS9 DQS9 DQS10 DQS10 DQS11 DQS11 DQS12 DQS12 DQS13 DQS13 DQS14 DQS14 DQS15 DQS15 DQS16 DQS16 DQS17 DQS17
Data Strobes 17:0 The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS through a 20 ohm to 10 Kohm resistor and DDR2 SDRAM mode registers programmed appropriately. Note: See block diagram for corresponding DQ signals
Data Sheet
13
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type I I I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS Serial Bus Clock This signal is used to clock data into and out of the SPD EEPROM. Serial Bus Data This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. Serial Address Select Bus 2:0 These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range Parity bits Note: Only for modules with parity bit for address and control bus. Not connected on non-parity registered modules. I/O Reference Voltage Reference voltage for the SSTL-18 inputs. EEPROM Power Supply Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt. I/O Driver Power Supply Power and ground for the DDR SDRAM Power Supply Power and ground for the DDR SDRAM Function
Pin or Ball No. Data Mask 125 134 146 155 202 211 223 232 164 EEPROM 120
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 SCL
Data Masks 8:0 The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. Note: x8 based module
119
SDA
I/O
OD
239 240 101 Parity 55
SA0 SA1 SA2 ERR_OUT PAR_IN
I I I O I
CMOS CMOS CMOS CMOS CMOS
Power Supplies 1 238
VREF VDDSPD
AI
--
PWR --
51, 56, 62, 72, 75, VDDQ 78, 170, 175,, 181, 191, 194 53, 59, 64, 67, 69, VDD 172, 178, 184,, 187, 189, 197
PWR --
PWR --
Data Sheet
14
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams Table 7 Pin Configuration of RDIMM (cont'd) Name Pin Buffer Type Type GND -- Function Ground Plane Power and ground for the DDR SDRAM
Pin or Ball No.
2, 5, 8, 11, 14, 17, VSS 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 Other Pins 19, 55, 68, 102, 137, 138, 173, 220, 221 195 77 NC
NC
--
Not connected Pins not connected on Infineon RDIMM's On-Die Termination Control 1:0 Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2-Ranks module
ODT0 ODT1
I I
SSTL SSTL
NC
NC
-- Note: 1-Rank modules
Table 8 SSTL CMOS OD
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation
Data Sheet
15
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Table 9 I O I/O AI PWR GND NU NC
Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable Not Connected
Abbreviation
Data Sheet
16
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 1
Pin Configuration for RDIMM (240 pins)
Data Sheet
17
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
2.2
Block Diagram
Figure 2 Notes
Block Diagram Raw Card A-F RDIMM (x72, 1Rank, x8) 3. CSR of register1 and DCS of register2 connects to
1. Unless otherwise noted, resistors are 22 5 % 2. S0 connects to DCS of register1 and CSR of register2.
VDD
4. RESET, PCK7 and PCK7 connect to both registers.
Data Sheet
18
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 3 Notes
Block Diagram Raw Card C-H RDIMM (x72, 1Rank, x4) 3. CSR of register1 and DCS of register2 connects to VDD. 4. RESET, PCK7 and PCK7 connect to both registers.
1. Unless otherwise noted, resistors are 22 5 % 2. S0 connects to DCS of register1 and CSR of register2.
Data Sheet
19
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 4 Notes
Block Diagram Raw Card B-G RDIMM (x72, 2Ranks, x8) 2. RS0 and RS1 alternate between the back and front sides of the DIMM. 20 Rev. 1.00, 2006-02 04212005-MF7V-DNO1
1. Unless otherwise noted, resistors are 22 5 % Data Sheet
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 5 Notes
Block Diagram Raw Card J RDIMM (x72, 2Ranks, x4) 3. S0 connects to DCS and S1 Connects to CSR on a pair of registers. S1 connects to DCS and S0 connects to CSR on another pair of registers. 4. RESET, PCK7 and PCK7 connect to all registers.
1. Unless otherwise noted, resistors are 22 5 % 2. RS0 and RS1 alternate between the bottom and surface sides of the DIMM. Data Sheet 21
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 6
Block Diagram Raw Card J Signal for Address and Command Parity Function
Data Sheet
22
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 7 Notes
Block Diagram Raw Card L RDIMM (x72, 2Ranks, x4) 3. S0 connects to DCS and S1 Connects to CSR on a pair of registers. S1 connects to DCS and S0 connects to CSR on another pair of registers. 4. RESET, PCK7 and PCK7 connect to all registers.
1. Unless otherwise noted, resistors are 22 5 % 2. RS0 and RS1 alternate between the bottom and surface sides of the DIMM. Data Sheet 23
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 8
Block Diagram Raw Card L Signal for Address and Command Parity Function
Data Sheet
24
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Pin Configuration and Block Diagrams
Figure 9 Notes
Block Diagram Raw Card N RDIMM (x72, 4Ranks, x8) 3. S2 and S3 have required pull up resistors (100K ), not indicated here. 4. A13-An have optional pull down resistors (100K ), not indicated here. 5. RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two of four Registers.
1. Unless otherwise noted, resistors are 22 5 % 2. S0 and S2 connects to DCS0, S1 and S3 to DCS1 on a Register A. S1 and S3 connects to DCS and S0 and S2 connects to CSR on another pair of Register.
Data Sheet
25
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
Table 10 Parameter
Absolute Maximum Ratings Symbol Values Min. Max. 2.3 2.3 2.3 95 V V V % -0.5 -1.0 -0.5 5 Unit Note/Test Condition
Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Storage Humidity (without condensation)
VIN, VOUT VDD VDDQ HSTG
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values maycause irreversible damage to the integrated circuit.
3.2
DC Operating Conditions
Table 11 Parameter
Operating Conditions Symbol Values Min. Max. +55 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG
PBar
0 0 -50 +69 10
HOPR
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature range all DRAM specification will be supported. Above 85 C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C case temperature before initiating self-refresh operation. 5) Up to 3000 m
Data Sheet
26
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 12 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol Values Min. Nom. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V
1) 2)
Unit
Notes
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low
3) In / Output Leakage Current -5 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
VREF + 0.125
-0.30
VDDQ + 0.3 VREF - 0.125
3.3
AC Characteristics
3.3.1
Speed Grades Definitions
Table 13
Speed Grade Definition Speed Bins for DDR2-667 DDR2-667 -3S 5-5-5 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) . 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Data Sheet
27
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 14
Speed Grade Definition Speed Bins for DDR2-533 DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Table 15
Speed Grade Definition Speed Bins for DDR2-400B DDR2-400B -5 3-3-3 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Data Sheet
28
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3.3.2
* * *
AC Timing Parameters
List of AC Timing Tables Table 16 "Timing Parameter by Speed Grade - DDR2-667" on Page 29 Table 17 "Timing Parameter by Speed Grade - DDR2-533" on Page 31 Table 18 "Timing Parameter by Speed Grade - DDR2-400" on Page 33 Timing Parameter by Speed Grade - DDR2-667 Symbol DDR2-667 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW Max. +450 -- 0.55 -- 0.55 -- -- -- -- -- +400 -- 240 + 0.25 -- -- -- -- ps -450 2 0.45 3 0.45 WR + tRP Unit Notes1)2)3)4)5)
6)7)
Table 16 Parameter
tAC tCCD tCH tCKE tCL tDAL tDELAY
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH
175 -- 0.35 -400 0.35 -- - 0.25 100 -- 0.2 0.2 MIN. (tCL, tCH) -- 275 0.6 200 2x
DQ and DM input hold time (differential data tDH(base) strobe) DQ and DM input hold time (single ended data strobe) DQ and DM input pulse width (each input)
tDH1(base)
tDIPW DQS output access time from CK / CK tDQSCK DQS input low (high) pulse width (write cycle) tDQSL,H DQS-DQ skew (for DQS & associated DQ tDQSQ
signals) Write command to 1st DQS latching transition
tCK
ps
tCK
ps
tDQSS
tCK
ps ps
DQ and DM input setup time (differential data tDS(base) strobe) DQ and DM input setup time (single ended data strobe) DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Clock half period
tDS1(base) tDSH tDSS
tCK tCK
tHP Data-out high-impedance time from CK / CK tHZ Address and control input hold time tIH(base) Address and control input pulse width tIPW
(each input) Address and control input setup time DQ low-impedance time from CK / CK
tAC.MAX
-- -- --
ps ps
tCK
ps ps
tIS(base) tLZ(DQ)
tAC.MIN
29
tAC.MAX
Data Sheet
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics Table 16 Parameter DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Write preamble Write postamble Write recovery time for write without AutoPrecharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Timing Parameter by Speed Grade - DDR2-667 (cont'd) Symbol DDR2-667 Min. Max. Unit Notes1)2)3)4)5)
6)7)
tLZ(DQS) tMRD tOIT tQH tQHS tREFI tRFC tRP tRPRE tRPST tRRD
tAC.MIN
2 0
tAC.MAX
-- 12 -- 340 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 --
ps
tCK
ns ps s s ns ns
8) 9)
tHPQ - tQHS
-- -- -- 105
tRP
0.9 0.40 7.5 10 7.5 0.35 x tCK 0.40 15
tCK tCK
ns ns ns
Internal Read to Precharge command delay tRTP
tWPRE tWPST tWR
WR
tCK tCK
ns
tWR/tCK
7.5 2 7 - AL 2 -- -- -- -- -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
tRFC +10
200
tCK
1) For details and notes see the relevant INFINEON component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) 0 C TCASE 85 C 9) 85 C < TCASE 95 C
Data Sheet
30
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 17 Parameter
Timing Parameter by Speed Grade - DDR2-533 Symbol DDR2-533 Min. Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- ps -500 2 0.45 3 0.45 WR + tRP Unit Notes1)2)3)4)
5)6)7)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 MIN. (tCL, tCH) -- 375 0.6 250 2x
tDH(base) tDH1(base)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data Sheet
tCK tCK
tDSS tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
31
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps
tAC.MIN tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns
tHP -tQHS
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics Table 17 Parameter Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Timing Parameter by Speed Grade - DDR2-533 (cont'd) Symbol DDR2-533 Min. Max. 400 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- ps s s ns ns
8) 9)
Unit
Notes1)2)3)4)
5)6)7)
tQHS tREFI tRFC tRP tRPRE tRPST tRRD tRTP
-- -- -- 105
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
tCK tCK
ns ns ns
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command WR
tCK tCK
ns
tWR/tCK
7.5 2 6 - AL 2 -- -- -- -- -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
tRFC +10
200
tCK
1) For details and notes see the relevant INFINEON component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) 0 C TCASE 85 C 9) 85 C < TCASE 95 C
Data Sheet
32
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 18 Parameter
Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. +600 -- 0.55 -- 0.55 -- -- -- -- -- +500 -- 350 + 0.25 -- -- -- -- ps -600 2 0.45 3 0.45 WR + tRP Unit Notes1)2)3)4)
5)6)7)
DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time
tAC tCCD tCH tCKE tCL tDAL
tCK tCK tCK tCK tCK
ns ps ps
Minimum time clocks remain ON after CKE tDELAY asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle)
tIS + tCK + tIH
275 -25 0.35 -500 0.35 -- - 0.25 150 -25 0.2 0.2 MIN. (tCL, tCH) -- 475 0.6 350 2x
tDH(base) tDH1(base)
DQ and DM input pulse width (each input) tDIPW
tCK
ps
tDQSCK tDQSL,H
tCK
ps
DQS-DQ skew (for DQS & associated DQ tDQSQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
tDQSS tDS(base)
tCK
ps ps
DQ and DM input setup time (single ended tDS1(base) data strobe) DQS falling edge hold time from CK (write tDSH cycle) DQS falling edge to CK setup time (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data Sheet
tCK tCK
tDSS tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
33
tAC.MAX
-- -- --
ps ps
tCK
ps ps ps
tAC.MIN tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns
tHP -tQHS
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics Table 18 Parameter Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Timing Parameter by Speed Grade - DDR2-400 Symbol DDR2-400 Min. Max. 450 7.8 3.9 -- -- 1.1 0.60 -- -- -- -- 0.60 -- ps s s ns ns
8) 9)
Unit
Notes1)2)3)4)
5)6)7)
tQHS tREFI tRFC
-- -- -- 105
tRP Read preamble tRPRE Read postamble tRPST Active bank A to Active bank B command tRRD
period
tRP
0.9 0.40 7.5 10 7.5 0.25 x tCK 0.40 15
tCK tCK
ns ns ns
Internal Read to Precharge command delay Write preamble
tRTP
tWPRE Write postamble tWPST Write recovery time for write without Auto- tWR
Precharge WR
tCK tCK
ns
Write recovery time for write with AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command
tWR/tCK
10 2 6 - AL 2 -- -- -- -- -- --
tCK
ns
tWTR tXARD tXARDS tXP tXSNR tXSRD
tCK tCK tCK
ns
tRFC +10
200
tCK
1) For details and notes see the relevant INFINEON component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. See notes 4)5)6)7) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) 0 C TCASE 85 C 9) 85 C < TCASE 95 C
Data Sheet
34
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3.3.3
ODT AC Electrical Characteristics
Table 19 Symbol
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 0.7 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Table 20 Symbol
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
35
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3.4
Currents Specifications and Conditions
Table 21 Parameter
IDD Measurement Conditions 1)2)3)4)5)6)7)8)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N
IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
36
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics Table 21 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are guaranteed up to TCASE of 85 C max.
IDD Measurement Conditions (cont'd)1)2)3)4)5)6)7)8)
Symbol
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 22 4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh) 7) All current measurements includes Register and PLL current consumption 8) For details and notes see the relevant INFINEON component data sheet
Table 22 Parameter LOW STABLE FLOATING
Definitions for IDD Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
inputs are stable at a HIGH or LOW level inputs are VREF = VDDQ /2 inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
SWITCHING
Data Sheet
37
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 23
IDD Specification for HYS72T[64/128/256]xx0HP-3S-A
HYS72T128000HP-3S-A HYS72T128020HP-3S-A HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A HYS72T64000HP-3S-A Unit Notes1)
Product Type
Organization
512MB 1 Rank x72 -3S
1GB 1 Rank x72 -3S Max. 1870 2130 690 1500 1320 940 700 1500 2940 3120 3120 700 90 3240
1GB 2 Ranks x72 -3S Max. 1070 1200 480 1290 1110 730 490 1290 1600 1690 1690 490 90 1750
2GB 2 Ranks x72 -3S Max. 1960 2220 780 2400 2040 1280 810 2400 3030 3210 3210 810 180 3330
2GB 2 Ranks x72 -3S Max. 1960 2220 780 2400 2040 1280 810 2400 3030 3210 3210 810 180 3330
2GB 4 Ranks x72 -3S Max. 1160 1290 570 2190 1830 1070 600 2190 1690 1780 1780 600 180 1840 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 2) 2) 2) 3)4) 3)4) 2)
Symbol
Max. 1020 1150 430 840 750 560 440 840 1560 1650 1650 440 45 1710
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD mode 4) Values for 0 C TCASE 85 C
Data Sheet
38
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
Table 24
IDD Specification for HYS72T[64/128/256]xx0HP-3.7-A
HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A HYS72T64000HP-3.7-A Unit Notes1)
Product Type
Organization
512MB 1 Rank x72 -3.7
1GB 1 Rank x72 -3.7 Max. 1670 1850 570 1220 1040 790 590 1220 2120 2210 2840 610 72 3030
1GB 2 Ranks x72 -3.7 Max. 950 1040 400 1050 870 620 420 1050 1180 1220 1540 440 72
2GB 2 Ranks x72 -3.7 Max. 1740 1920 640 1940 1580 1080 680 1940 2190 2280 2920 720 144
2GB 4 Ranks x72 -3.7 Max. 1020 1110 470 1770 1410 910 510 1770 1250 1290 1610 550 144 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3) 3) 3) 3) 2) 2) 3)4) 3)4)
Symbol
Max. 920 1010 370 690 600 470 380 690 1140 1190 1500 380 36 1590
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
1) 2) 3) 4)
2) 1630 3100 1700 mA Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. The other rank is in IDD2P Precharge Power-Down Standby Current mode Both ranks are in the same IDD mode Values for 0 C TCASE 85 C
Data Sheet
39
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3.4.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used: Table 25 Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
1) x4 & x8 (1 kB page size) 2) x16 (2 kB page size), not on 256M components
IDD Measurement Test Conditions for DDR2-667
Symbol CL(IDD) -3S DDR2-667D 5 3.75 15 60 7.5 10 45 70000 15 105 7.8 Unit
tCK
ns ns ns ns ns ns ns ns ns s
x8
1) 2)
x16
tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tRFC(IDD) tREFI
Table 26 Parameter
IDD Measurement Test Conditions for DDR2-533
Symbol -3.7 DDR2-533C 4 3.75 15 60 7.5 10 45 70000 15 105 7.8 Unit
CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval
1) x4 & x8 (1 kB page size) 2) x16 (2 kB page size), not on 256M components
x8
1) 2)
x16
CL(IDD) tCK(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tRRD(IDD) tRAS.MIN(IDD) tRAS.MAX(IDD) tRP(IDD) tRFC(IDD) tREFI
tCK
ns ns ns ns ns ns ns ns ns s
Data Sheet
40
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Electrical Characteristics
3.4.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 27 Parameter Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING ODT current per terminated pin
Symbol Min.
Typ. 6 3 9 12 6 18
Max. Unit 7.5 3.75 15 7.5 22.5
EMRS(1) State
IODTO
5 2.5 7.5 10 5 15
mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 1, A2 = 0
11.25 mA/DQ A6 = 1, A2 = 1
Active ODT current per DQ IODTT ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
Data Sheet
41
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * * * Table 28 "SPD Codes for HYS72T[64/128]xxxHP-3S-A" on Page 42 Table 29 "SPD Codes for HYS72T256xx0HP-3S-A" on Page 46 Table 30 "SPD Codes for HYS72T[64/128/256]xx0HP-3.7-A" on Page 50 SPD Codes for HYS72T[64/128]xxxHP-3S-A HYS72T128000HP-3S-A HYS72T128020HP-3S-A 1 GByte x72 2 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0A 61 48 00 05 30 45 06 82 08 08 00 0C 04 Rev. 1.00, 2006-02 04212005-MF7V-DNO1 HYS72T64000HP-3S-A 512MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0A 60 48 00 05 30 45 06 82 08 08 00 0C 04 42
Table 28
Product Type
Organization
1 GByte x72 1 Rank (x4) PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0B 60 48 00 05 30 45 06 82 04 04 00 0C 04
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device
Data Sheet
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 28 SPD Codes for HYS72T[64/128]xxxHP-3S-A (cont'd) HYS72T128000HP-3S-A HYS72T128020HP-3S-A 1 GByte x72 2 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 38 01 01 05 03 3D 50 50 60 3C 1E 3C 2D 80 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 Rev. 1.00, 2006-02 04212005-MF7V-DNO1 HYS72T64000HP-3S-A 512MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Description Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes PC2-5300R- 555 Rev. 1.2 HEX 38 01 01 04 03 3D 50 50 60 3C 1E 3C 2D 80 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18
Product Type
Organization
1 GByte x72 1 Rank (x4) PC2-5300R- 555 Rev. 1.2 HEX 38 01 01 05 03 3D 50 50 60 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns]
43
Data Sheet
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 28 SPD Codes for HYS72T[64/128]xxxHP-3S-A (cont'd) HYS72T128000HP-3S-A HYS72T128020HP-3S-A 1 GByte x72 2 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 22 0F 53 78 4B 2E 26 26 2B 1B 4A 20 22 C4 8C 68 94 12 49 C1 00 00 00 00 00 00 00 Rev. 1.00, 2006-02 04212005-MF7V-DNO1 HYS72T64000HP-3S-A 512MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Description PC2-5300R- 555 Rev. 1.2 HEX 22 0F 53 78 4B 2E 26 26 2B 1B 4A 20 22 C4 8C 68 94 12 47 C1 00 00 00 00 00 00 00
Product Type
Organization
1 GByte x72 1 Rank (x4) PC2-5300R- 555 Rev. 1.2 HEX 22 0F 53 78 4B 2E 26 26 2B 1B 4A 20 22 C4 8C 68 94 12 C2 C1 00 00 00 00 00 00 00
tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8)
Data Sheet
44
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 28 SPD Codes for HYS72T[64/128]xxxHP-3S-A (cont'd) HYS72T128000HP-3S-A HYS72T128020HP-3S-A 1 GByte x72 2 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX xx 37 32 54 31 32 38 30 32 30 48 50 33 53 41 20 20 20 20 0x xx xx xx xx 00 Rev. 1.00, 2006-02 04212005-MF7V-DNO1 HYS72T64000HP-3S-A 512MB x72 1 Rank (x8) Label Code JEDEC SPD Revision Byte# 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number PC2-5300R- 555 Rev. 1.2 HEX xx 37 32 54 36 34 30 30 30 48 50 33 53 41 20 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
1 GByte x72 1 Rank (x4) PC2-5300R- 555 Rev. 1.2 HEX xx 37 32 54 31 32 38 30 30 30 48 50 33 53 41 20 20 20 20 0x xx xx xx xx 00
99 - 127 Not used
Data Sheet
45
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes
Table 29
SPD Codes for HYS72T256xx0HP-3S-A HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A 2 GByte x72 4 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0A 63 48 00 05 30 45 06 82 08 08 00 0C 04 38 01 01 07 03 3D 50 50 60 Rev. 1.00, 2006-02 04212005-MF7V-DNO1
Product Type
Organization
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4) PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0B 61 48 00 05 30 45 06 82 04 04 00 0C 04 38 01 01 07 03 3D 50 50 60
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-5300R- 555 Rev. 1.2 HEX 80 08 08 0E 0B 61 48 00 05 30 45 06 82 04 04 00 0C 04 38 01 01 07 03 3D 50 50 60 46
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns]
Data Sheet
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 29 SPD Codes for HYS72T256xx0HP-3S-A (cont'd) HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A 2 GByte x72 4 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 3C 1E 3C 2D 80 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 22 0F 53 78 4B 2E 26 26 2B Rev. 1.00, 2006-02 04212005-MF7V-DNO1
Product Type
Organization
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4) PC2-5300R- 555 Rev. 1.2 HEX 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 22 0F 53 78 4B 2E 26 26 2B
Label Code JEDEC SPD Revision Byte# 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Description
PC2-5300R- 555 Rev. 1.2 HEX 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 00 3C 69 80 18 22 0F 53 78 4B 26 26 2B
tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) 47
T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) 2E
Data Sheet
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 29 SPD Codes for HYS72T256xx0HP-3S-A (cont'd) HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A 2 GByte x72 4 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 1B 4A 20 22 C4 8C 68 94 12 4D C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 30 34 Rev. 1.00, 2006-02 04212005-MF7V-DNO1
Product Type
Organization
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4) PC2-5300R- 555 Rev. 1.2 HEX 1B 4A 20 22 C4 8C 68 94 12 C5 C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 32 32
Label Code JEDEC SPD Revision Byte# 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Description T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8
PC2-5300R- 555 Rev. 1.2 HEX 1B 4A 20 22 C4 8C 68 94 12 C5 C1 00 00 00 00 00 00 00 xx 37 32 54 32 35 36 30 32
Data Sheet
48
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 29 SPD Codes for HYS72T256xx0HP-3S-A (cont'd) HYS72T256020HP-3S-A HYS72T256220HP-3S-A HYS72T256040HP-3S-A 2 GByte x72 4 Ranks (x8) PC2-5300R- 555 Rev. 1.2 HEX 30 48 50 33 53 41 20 20 20 20 0x xx xx xx xx 00 Rev. 1.00, 2006-02 04212005-MF7V-DNO1
Product Type
Organization
2 GByte x72 2 Ranks (x4)
2 GByte x72 2 Ranks (x4) PC2-5300R- 555 Rev. 1.2 HEX 30 48 50 33 53 41 20 20 20 20 0x xx xx xx xx 00
Label Code JEDEC SPD Revision Byte# 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-5300R- 555 Rev. 1.2 HEX 30 48 50 33 53 41 20 20 20 20 0x xx xx xx xx 00
99 - 127 Not used
Data Sheet
49
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes
Table 30
SPD Codes for HYS72T[64/128/256]xx0HP-3.7-A HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A x72 PC2- 4200R- 444 HEX 80 08 08 0E 0A 63 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 07 03 3D 50 HYS72T64000HP-3.7-A 512MB x72 1 Rank (x8)
Product Type
Organization
1 GByte 1 GByte 2 GByte 2 GByte x72 1 Rank (x4) PC2- 4200R- 444 HEX 80 08 08 0E 0B 60 48 00 05 3D 50 06 82 04 04 00 0C 04 38 01 01 05 03 3D 50 x72 x72 2 Ranks 2 Ranks 4 Ranks (x8) (x4) (x8) PC2- 4200R- 444 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 05 03 3D 50 PC2- 4200R- 444 HEX 80 08 08 0E 0B 61 48 00 05 3D 50 06 82 04 04 00 0C 04 38 01 01 07 03 3D 50
Label Code
PC2- 4200R- 444 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 06 82 08 08 00 0C 04 38 01 01 04 03 3D 50 50
JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns]
Data Sheet
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 30 SPD Codes for HYS72T[64/128/256]xx0HP-3.7-A (cont'd) HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A x72 PC2- 4200R- 444 HEX 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F HYS72T64000HP-3.7-A 512MB x72 1 Rank (x8) Label Code PC2- 4200R- 444 HEX 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F
Product Type
Organization
1 GByte 1 GByte 2 GByte 2 GByte x72 1 Rank (x4) PC2- 4200R- 444 HEX 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F x72 x72 2 Ranks 2 Ranks 4 Ranks (x8) (x4) (x8) PC2- 4200R- 444 HEX 50 60 3C 1E 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F PC2- 4200R- 444 HEX 50 60 3C 1E 3C 2D 01 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3F
JEDEC SPD Revision Byte# 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Description
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2
tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0)
Data Sheet
51
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 30 SPD Codes for HYS72T[64/128/256]xx0HP-3.7-A (cont'd) HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A x72 PC2- 4200R- 444 HEX 22 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 1F C1 00 00 00 00 00 00 00 xx 37 32 HYS72T64000HP-3.7-A 512MB x72 1 Rank (x8) Label Code PC2- 4200R- 444 HEX 22 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 19 C1 00 00 00 00 00 00 00 xx 37 32
Product Type
Organization
1 GByte 1 GByte 2 GByte 2 GByte x72 1 Rank (x4) PC2- 4200R- 444 HEX 22 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 94 C1 00 00 00 00 00 00 00 xx 37 32 x72 x72 2 Ranks 2 Ranks 4 Ranks (x8) (x4) (x8) PC2- 4200R- 444 HEX 22 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 1B C1 00 00 00 00 00 00 00 xx 37 32 PC2- 4200R- 444 HEX 22 1E 1E 24 17 34 1E 20 C4 8C 61 78 12 97 C1 00 00 00 00 00 00 00 xx 37 32
JEDEC SPD Revision Byte# 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Description T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2) JEDEC ID Code of Infineon (3) JEDEC ID Code of Infineon (4) JEDEC ID Code of Infineon (5) JEDEC ID Code of Infineon (6) JEDEC ID Code of Infineon (7) JEDEC ID Code of Infineon (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2
Data Sheet
52
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
SPD Codes Table 30 SPD Codes for HYS72T[64/128/256]xx0HP-3.7-A (cont'd) HYS72T128000HP-3.7-A HYS72T128020HP-3.7-A HYS72T256220HP-3.7-A HYS72T256040HP-3.7-A x72 PC2- 4200R- 444 HEX 54 32 35 36 30 34 30 48 50 33 2E 37 41 20 20 20 0x xx xx xx xx 00 HYS72T64000HP-3.7-A 512MB x72 1 Rank (x8) Label Code PC2- 4200R- 444 HEX 54 36 34 30 30 30 48 50 33 2E 37 41 20 20 20 20 0x xx xx xx xx 00
Product Type
Organization
1 GByte 1 GByte 2 GByte 2 GByte x72 1 Rank (x4) PC2- 4200R- 444 HEX 54 31 32 38 30 30 30 48 50 33 2E 37 41 20 20 20 0x xx xx xx xx 00 x72 x72 2 Ranks 2 Ranks 4 Ranks (x8) (x4) (x8) PC2- 4200R- 444 HEX 54 31 32 38 30 32 30 48 50 33 2E 37 41 20 20 20 0x xx xx xx xx 00 PC2- 4200R- 444 HEX 54 32 35 36 32 32 30 48 50 33 2E 37 41 20 20 20 0x xx xx xx xx 00
JEDEC SPD Revision Byte# 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2
99 - 127 Not used
Data Sheet
53
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
5
Package Outlines
Figure 10
Package Outline Raw Card A-F L-DIM-240-11
Data Sheet
54
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
Figure 11
Package Outline Raw Card C-H L-DIM-240-13
Data Sheet
55
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
Figure 12
Package Outline Raw Card B-G L-DIM-240-12
Data Sheet
56
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
Figure 13
Package Outline Raw Card J L-DIM-240-20
Data Sheet
57
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
Figure 14
Package Outline Raw Card L L-DIM-240-40
Data Sheet
58
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Package Outlines
Figure 15
Package Outline Raw Card N L-DIM-240-44
Data Sheet
59
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
HYS72T[64/128/256]xx0]HP-[3S/3.7]-A Registered DDR2 SDRAM Modules with parity
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
6
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
description together with possible values and coding explanation is listed for modules in Table 32 and for components in Table 33.
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 31 provides examples for module and component product type number as well as the field number. The detailed field Table 31 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 32 1 2 3 4 HYS HYB 2 64 18 3 T T 4 64 512 5 0 16
Example for
6 2
7 0 0
8 K A
9 M C
10 -5 -5
11 -A
DDR2 DIMM Nomenclature Values Coding HYS Constant Non-ECC ECC DDR2 512 MByte 1 GByte 2 GByte Look up table 1, 2, 4 Look up table Look up table
Field Description INFINEON Modul Prefix
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Module Data Width 64 [bit] 72 DRAM Technology T Memory Density per I/O [Mbit]; Module Density1) Raw Card Generation 64 128 256 0 .. 9
Table 33 1 2 3 4
DDR2 DRAM Nomenclature Values Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
Field Description
INFINEON HYB Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] 18 T 256 512 1G 2G
5 6 7 8 9
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, LeadFree Status Module Type A .. Z D M R P U F
5+6 SO-DIMM Micro-DIMM Registered Registered with parity Unbuffered Fully Buffered PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second 10 7 8 9
Number of I/Os
40 80 16
Product Variations 0 .. 9 Die Revision Package, Lead-Free Status Speed Grade A B C F -2.5 -3 -3S -3.7 -5
10
Speed Grade
-2.5 -3 -3S -3.7 -5
11
Die Revision
-A -B
Data Sheet
60
Rev. 1.00, 2006-02 04212005-MF7V-DNO1
www.infineon.com
Published by Infineon Technologies AG

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